SAR  ADC

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market for medium to high resolution ADCs. SAR ADCs provide up to 5Msps sampling rates with resolutions from 8 to 18 bits. The SAR architecture allows for high performance, low power ADCs to be packaged in small form factors for today's demanding applications.
This paper will explain how the SAR ADC operates using a binary search algorithm to converge on the input signal. It also provides an explanation for the heart of the SAR ADC, the capacitive DAC and also the high-speed comparator. Finally, the article will contrast the SAR architecture against pipeline, flash ADCs.
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 mega-samples per second (Msps). SAR ADCs most commonly range in resolution from 8 to 16 bits and provide low power consumption as well as a small form factor. This combination makes them ideal for a wide variety of applications, such as portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition.
As the name implies, the SAR ADC basically implements a binary search algorithm. Therefore, while the internal circuitry may be running at several megahertz (MHz), the ADC sample rate is a fraction of that number due to the successive-approximation algorithm.

Although there are many variations in the implementation of a SAR ADC, the basic architecture is quite simple (see Figure 1). The analog input voltage (V_IN) is held on a track/hold. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to '1'). This forces the DAC output (V_DAC) to be V_REF/2, where V_REF is the reference voltage provided to the ADC. A comparison is then performed to determine if V_IN is less than or greater than V_DAC. If V_IN is greater than V_DAC, the comparator output is a logic high or '1' and the MSB of the N-bit register remains at '1'. Conversely, if V_IN is less than V_DAC, the comparator output is a logic low and the MSB of the register is cleared to logic '0'. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete, and the N-bit digital word is available in the register.

Figure 1. Simplified N-bit SAR ADC architecture

Figure 2 shows an example of a 4-bit conversion. The y-axis (and the bold line in the figure) represents the DAC output voltage. In the example, the first comparison shows that V_IN < V_DAC. Thus, bit 3 is set to '0'. The DAC is then set to 0100₂ and the second comparison is performed. As V_IN > V_DAC, bit 2 remains at '1'. The DAC is then set to 0110₂, and the third comparison is performed. Bit 1 is set to '0', and the DAC is then set to 0101₂ for the final comparison. Finally, bit 0 remains at '1' because V_IN > V_DAC.

Figure 2. SAR operation (4-bit ADC example)

Notice that four comparison periods are required for a 4-bit ADC. Generally speaking, an N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete. This explains why these types of ADCs are power- and space-efficient, yet are rarely seen in speed-and-resolution combinations beyond a few Msps at 14 to 16 bits. Some of the smallest ADCs available on the market are based on the SAR architecture. The MAX1115-MAX1118 series of 8-bit ADCs as well as their higher-resolution counterparts, the MAX1086 and the MAX1286 (10 and 12 bits, respectively), fit in tiny SOT23 packages measuring 3mm by 3mm.
One other feature of SAR ADCs is that power dissipation scales with the sample rate, unlike flash or pipelined ADCs, which usually have constant power dissipation versus sample rate. This is especially useful in low-power applications or applications where the data acquisition is not continuous (for example, PDA digitizers).

The two critical components are the comparator and the DAC. As we shall see later, the track/hold shown in Figure 1 can be embedded in the DAC and may not be an explicit circuit.
A SAR ADC's speed is limited by:

1. The settling time of the DAC, which must settle to within the resolution of the overall converter, for example, 1/2LSB

2.  The comparator, which must resolve small differences in V_IN and V_DAC within the specified time

3. ·The logic overhead